Clock Managers

The Spartan 6 family had a DCM_CLKGEN clock manager, but this primitive is obsolete for the Zynq 7 series. Here are clocking guides to help navigate that:

https://xilinx.eetrend.com/files-eetrend-xilinx/forum/201102/1621-3006-ug382.pdf
http://ece-research.unm.edu/pollard/classes/595/K7/ug472_7Series_Clocking.pdf

DCM_SP and DCM_CLKGEN are no longer available and their functionality is now supported in the MMCMs and PLLs. The Spartan-6 FPGAs DCM_CLKGEN is not directly supported in the 7 series FPGAs. Use MMCM or PLL with low bandwidth for input jitter filtering. Dynamic reprogramming of the M/D values can also be accomplished using the DRP reference design for the MMCM or PLL.

Synthesizing a Black Box

What is a Black Box? In synthesis, it is part of your design which is empty (contains no code). It might be an empty Verilog module instance, or an empty VHDL component instance. A missing piece of code occurs when you use a pre-written piece of design, typically a piece of IP.

What about this error: Could not resolve non-primitive black box cell 'RAMB16BWER'
This may be a result of migrating an older design that uses older cores that are no longer available, like the BRAM above. See https://support.xilinx.com/s/question/0D52E00006hpn44SAA/migrate-verilog-spartan-6-design-to-artix-100t?language=en_US