XRFdc is the prefix used for all aspects of the RF Data Converter IP. Drivers supported under Linux and bare-metal.

Architecture

MPSoC and RFSoC use the same PS ARM Cortex A53. There are four power domains: PS battery (RTC, battery backed RAM), PS low power (OCM, USB, ...), PS full power (APU, L2 cache, debug, ...), PL power. Boot interfaces are quad SPI flash, SD 3.0, NAND flash, eMMC (managed NAND).

The idea with the RFSoC is that ADC and DAC tech has come far enough that paired with good filters, single board high perf SDR is now a possibility. It reaches 4 GHz bandwidth with 8x 4Gsps ADCs or 16x 2Gsps ADCs.

SD-FEC is a hard core unit using LDPC or Turbo coding (note that decode is more compute intensive than encode, just like spread-spectrum mod/demod).

Data Converter

AXI lite control with AXI Stream data for ADC/DAC. In API, channel/block/slice have same meaning, with each representing an ADC or DAC. The clock can be high freq external, or use on board PLC. DDC is optional to get down to baseband. The ADC/DAC can be used in PL-only design because the cores are configured at startup. A SW API adds monitoring and interrupts. No R/W functions in the Data Converter API, because the rates are so high for the PS. Separate AXIS paths through FIFOs exist for moving the data. (And I assume DMA is a big piece of this). PG269 document provides API information.

ADC Basics

For a 12-bit ADC, SNR is close to 74dB. SNR here refers to noise in a whole band.
A crest factor is the peak voltage over RMS voltage
the integral non-linearity is a deviation from ideal code transition point, quantized output deviations
noise spectral density is the PSD of noise OR noise power per unit bandwidth; AKA noise floor distributed across all frequencies
noise figure is the lowest/weakest RX strength of signal that can still be recovered successfully at receiver
SFOR = comparison of wanted and unwanted tones in FFT

Doubling the sampling rate can result is a 3dB reduction in the noise floor because the noise is spread over a wider bandwidth. But sampling is said to be more noisy than mixing - why?

ADC Architecture

Gen3 devices have 14-bit resolution. Programmable threshold flags are available. One PLL per tile, also decimation filter and complex mixers with 48-bit NCO. Real-time control of NCO and real-time over-range, over-threshold, orver-voltage outputs. Over-voltage results in buffer shutdown for protection (automatic DSA).

input -> threshold detection -> quadrature modulator correction gain/phase -> crossbar -> mixer -> decimation

The QMC stops degradation with a gain factor of 0-2 and phase factor +/- 26 degrees.

Built-in DSP functions are:

detection with programmed threshholds
compensation with QMC
DDC mixing and decimation

Coarse or fine mixing available. Can do real to I/Q or I/Q to I/Q. Runtime mixer settings changes available via API. The DDC gives you a lower frequency at lower sampline rate to simplify remaining compute. Decimation is a combination of filtering (like anti-aliasing, FIR filter stages) and downsampling. i.e. input signal -> oversample to get all the data -> downsample to reduce the compute work.

IP Core Configuration

Don't use a Verilog template, use IP Catalog.
Mixer types are bypass, coarse, fine (-10Ghz to 10Ghz NCO).
Calibration model is best for freq at 1/2 of sampling.
Independent I/Q decimation. (Input -> Mixer -> I decimation, Q decimation separately)

SW Driver

Each tile has a PLL and DDC

LibMetal Xilinx open source SW stack with APIS for devices w/ interrupts and memory access. Drivers for ADCs and DACs can be included in BSP and they are the same for bare metal and Linux. A sticky bit is a flag that requires manual clearing. Using threshold control with API enables setting up an AGC. The API abstracts the IP control registers.

Implementation Details

For RF-ADC typically use AC coupling. DC is available for zero IF mode. If using DC, must use VCM pin to align internal common mode voltage with external driving circuit common mode voltage.

Cal mode 2 is for anything other than input freq of Nyquist +/- 30%.

DAC Basics

DAC can degrade a signal, quantization error is present as with ADC. Programmed output is some proportion of reference V or I. INC error adds harmonies and spurious signals to output. NSD is more important than actual SNR. It allows comparing noise performance of data converters with distinct sample rates.

balun = balanced to unbalanced, 50 ohm unbal and 100 ohm bal impedances, a bridge between balanced and unbalanced transmission lines (B to U), commonly used in antenna systems to connect a balanced antenna (like a dipole) to an unbalanced coaxial cable
dBFS = dB full-scale
de-sensing = losing sensitivity
DUC = digital up-converter
HDR = high dynamic range, receiving strongest and weakest signals
INC = integral non-linearity error, describes the deviation of the actual DAC output curve from a perfectly straight line across its entire range
MTS = multi-tile sync
PEP = peak envelope power, direct power setting for signal strength
resolution = step size
speed = sample rate
TDR = total dynamic range, strongest signal to receive
THD = total harmonic distortion, sum of harmonic power
VOP = variable output power

Higher resolutions do not equate to lower noise.

DAC Architecture

Each tile has 4 DACs at 10Gsps for Gen3 chips and on-chip calibrated 100 ohm termination.

The DUC maintains freq info, but moves the center freq. Uses interpolation filters to implement up-sampling and fill in the data points at higher freq.

Max data rate of DAC is limited by DUC, but it can also be bypassed.

Matching converter latency across tiles is critical. One PLL per tile, so all converters in a tile will use same sampling clock. Best phase noise achieved if reference divider can be 1 (values 1 to 4).

SYSREF is used for multi-channel sync, cannot use PLL for multi-tile. Each ADC/DAC tile has its own clock input. The PLL can be bypassed.

Design and Implementation

IP integrator flow recommended.

For analog values in simulation, a 64-bit Verilog data type is used.

RF Evalulations

Ordered intermod products are spikes in the spectrum whose height indicates how well the device performs, an ideal system wouldn't have any. Intermod products are similar to harmonics and come from same root cause, but the former refer specifically to double tones. The baluns do not affect this. Lowering PEP also lowers intermod products.

Want NSD to be as low as possible (negative).

What is a spurious entity? Not harmonically related signal component, so it doesn't necessarily go away if signal is gone.

Intermod Products example

F1 = 10 Mhz, F2 = 15 Mhz
2nd order products are F1+F2 = 25Mhz and F2-F1 = 5 Mhz
3rd order products are 2*F1+/-F2 or F1+/-2*F2, etc, like 35Mhz, 40Mhz, 5Mhz, 10Mhz

What is the Nyquist zone?

Nyquist is half the sampling rate, and any signal above that will be aliased. Nyquist zones subdivide the spectrum into uniformly spaced regions at intervals of the NF, fs/2. Each zone contains a copy of the spectrum or a mirror image. Spurs that are past the boundary of Nyquist zone fold back into previous zone.

RFDC (RF Data Converter)

It acts as a bridge between the analog RF domain and the digital domain by converting RF signals to digital data and vice versa.

harmonic = signal distortion, and spurs are harmonics of input signal, HDn is the nth order harmonic spur
frequency planning = set the fs to plan around HD2 and HD3 so they don't fold back in to Nyquist zone.

Higher sampling rates improve system perf. To achieve this, you can interleave multiple ADCs, for example the Xilinx RFDC is x4 or x8 ADCs.

HD2 - HD5 are lower order harmonics, HD6 higher order

Oversampling and decimation have the effect of enlarging a zone.

What if you want to shift the DAC output freq to center RF freq?

Set the mixer NCO freq as you want, change from 0 (can that be called an offset?) as the mixer does freq translations.