SPI

SPI is a pretty open protocol, so vendors have lots of freedom in implementing things. This leads often to a need to customize driver work. For example, in the iMX6 SPI peripheral you have an option to set burst lengths and control whether the slave select negates between bursts.

SPI is a four-wire bus. It uses a select line for addressing. 20 Mbps is the max data rate. The master drives three of the lines, with the slave driving one. There are four clock modes, numbered 0 through 3. These modes determine the steady state of the SCLK line, high or low, and the clock edge choices for the sampling and driving of data. Usually set with two fields CPHA and CPOL (phase and polarity) with a 0 or 1 to each.

Another way this is described by some protocol analyzers is that a transaction is defined by three parameters: clock polarity, clock phase, and bit order and the three need to be set the same between master and slave.

With SPI drivers, pay particular attention to the clock phase and polarity settings, as well as the leading and trailing delay settings. That is, the time between slave select and first clock, and then last clock edge and end of slave select.

SPI full duplex mode means that data is sent back over the slave out in response to a command immediately, as part of the same initiating frame. This is a very fast turn-around time, and looks as if the master gets an answer before it is done asking the question. This can be done in cases, for example, where a read command and address go out at the beginning of the frame with the rest of the bits being ignored.

SPI basics: https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi/all

What is 3-wire SPI?

Some chips offer this option. It combines the two lines into one bi-directional data I/O line. Note this is a big change taking SPI from a uni-directional interface to bi-directional interface at the physical layer.

What is Quad SPI?

Normal SPI has only one data line in each direction between master and slave, MOSI and MISO. Dual SPI changes this to be two bi-directional pins, and quad SPI makes four bi-directional pins.

DMA Option

Some SPI modules allow DMA transactions. The TriCore has you include the basic module configuration word as the first 32-bits of data in the DMA buffer, so that it takes that first word and writes it to the basic control register to set up the proper parameters for this particular transaction, then inserts the remaining data from the TX buffer into the FIFO to go out over the data line. The idea is you can change the channel/destination/format on each data transaction, by attaching a "header" to the data itself rather than needing to do it via separate CPU instructions.

Driver Architecture Notes

Some chips will send data back on the same transaction the master initiates, and this can be treated as a response. You may be able to detect a problem with the transaction in this response and note the error at the peripheral layer driver or similar. For example, if the chip is addressable and the address is repeated back but gives an invalid value which would be clearly different than what was sent. These can be compared to find a problem.

But if you have separate R/W commands and only data is returned, then any data could be valid as far as the lowest layer is concerned. In this case, you probably need to handle error checking at a higher device management layer where you are examining the possible data values for a specific register in the chip.

I2C

I2C is a two-wire bus (data/address and clock) with both being bidirectional. Can have multiple masters and slaves. Both lines are open-drain and require pull-up resistors. Data rate maximums are 3.4 Mbps or 5 Mbps for extended mode options.

Open drain allows there to be multiple masters on the same bus. If two masters try to transmit at the same time with push-pull drivers, they can damage each other, and even if they don't it's hard to tell which master will win. Open drain acts as a "wired AND", which makes it easy to share the line and arbitrate collisions.

Typical voltages used are +5 V or +3.3 V, although systems with other voltages are permitted.

I2C has a built-in ack like system, but SPI does not.

Addressing

I2C is known as the addressable bus, while SPI is known as the selected bus, but this isn't strictly true. You can also use addresses in SPI.

So more important distinctions would be the speed and the fact that SPI is a single master bus while I2C is multi-master. Also SPI with it's higher dedicated directional wire count can give you full-duplex communication while I2C is by definition half-duplex.