Tcl

To dump the shell PATH variable: exec echo [set env(PATH)]

To set a variable equal to the value of an executable expression: set fd [open "filename"]

To check and see if a folder exists use: if {[file isdirectory <name>]} {

Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

reset_project = Tcl command cleans out all the output files generated during synthesis, simulation and implementation and resets the state of the project to the start of the design flow

Handy Tcl command to show system clock schematic: show_schematic [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ CLK.*.* } ]

The path characteristics fall into four main categories: timing, logic, physical, and property. You can find the definition of each characteristics in the command long help. Tcl Command: report_design_analysis -help

To delete a directory along with everything in that directory, recursively:
file delete -force -- $pathname

ipx and ipgui

ipx::package_project

ipx is not a command of TCL itself, but something Vivado's TCL libraries have. That means ipx is a Tcl namespace and package_project is a procedure defined within that namespace.

The custom IP packager struggles to see that you've made any changes to the ports at the top level of the block. To force it, use the Tcl command: ipx::merge_project_changes ports [ipx::current_core] which should work in either temporary Edit mode or standing Vivado instance mode.

You can get help with: help ipx::* and help ipgui:**

Upgrade All IP

upgrade_ip [get_ips]

Setting and Getting Parameters

Examples

set_part xcvu095-ffva2104-2-e
set_property target_language Verilog [current_project]
set_property board_part xilinx.com:vcu108:part0:1.6 [current_project]
set_property default_lib xil_defaultlib [current_project]

Using Tcl to take control of Vivado project

This is as straightforward as Xilinx wants it to sound apparently. Here's an interesting write up from a fellow that was fed up with the obstacles: https://github.com/MaxDZ8/goodbye-vivproj/